1. Field of the Invention
This invention relates to integrated-circuit (IC) amplifiers. More particularly, this invention relates to IC amplifiers of the type comprising a successive series of cascaded stages with current feedback.
2. Description of the Prior Art
Most operational amplifiers of the integrated complementary type (i.e., having symmetrical NPN/PNP transistors) have been basically of a single gain-stage design. FIG. 1 illustrates a prior art circuit configuration as might be used in a single stage feedback amplifier design.
In this circuit, transistors Q1/Q2 provide level shifting to the bases of inverting input transistors Q3/Q4. Using equal emitter areas for pairs Q1/Q3 and Q2/Q4, the collector currents for Q3/Q4 will be approximately equal. Neglecting finite beta's and transistor output conductance, the collector current Ic(Q3)=Ic(Q4) with IPP=INP and Vn is approximately zero for Vp=0. Second order PNP/NPN mismatch effects such as output conductance (PNP/NPN Early Voltages or VA's), DC beta, IS, etc., are also neglected in this analysis. Assuming matched transistor and resistor pairs Q5/Q7 and RE5/RE7 respectively, 1:1 mirror action results with Q7's collector current (IQ0) approximately equal to IQ1. Likewise, with Q6/Q7 and RE6/RE7 matched, IQ0 will closely equal IQ1. With the loop closed from the output of the buffer amplifier A3, negative feedback action results.
Any initial input signal (Vp) variation results in a difference current (ie) at the emitters of common base transistors Q3/Q4. This error current is mirrored and summed at the common collector ports of Q7/Q8, resulting in a voltage transformation (Vo') equal to ie*Z2, where Z2 is the equivalent buffer input port impedance of amplifier A3. This impedance is equal to the total parasitic capacitance CD in parallel with the total parasitic resistance R2 at the input port of buffer amplifier A3 plus any fixed capacitance necessary to maintain adequate loop stability. The total equivalent impedance is designated Z2.
Vo' is buffered by A3 resulting in an output signal (Vo) approximately equal to Vo'. This signal is servoed back through feedback resistor RF which results in a final signal error current Vo/To, where To is the transimpedance gain of the amplifier and is approximately equal to Z2. An input-referred voltage error (Vp-Vn) is also created by the ie*Zi drop that results, where Zi is the open loop inverting input impedance. Its value can be approximated (neglecting Q3/Q4's output conductance) as 1/2 times the thermal emitter resistance of Q3 (or Q4); that is, it is equal to 1/2*gmf. The magnitude of these two errors depends on both the open loop voltage gain (Ao) and transimpedance gain (To) of the amplifier.
The quasi-DC closed loop gain (i.e., gain at frequencies very close to zero) can be expressed as: ##EQU1## Where Ao=gmf.div.2*R2 To=R2 and G=1+RF/RN (non-inv) R2 is the real component of Z2.
Using the above gain expression, the input referred error signal can be expressed as: EQU Vp-Vo/G=G/Ao+RF/To
Being of a "single stage" design, the open loop gain (To and Ao) of the FIG. 1 circuit will generally be lower than a true two-stage amplifier. Note that Q5/RE5 with parallel Q7/RE7 form a 1:1 current mirror and no amplification is generated. Though current gains (IQ0/IQ1) greater than one can be realized, excessive power would quickly result due to both the magnitude of the signal current and quiescent collector current of Q7/Q8 increasing equally. Though higher loop gain could be realized by using a quad or modified Wilson for the mirror stages (not shown), output voltage swing range would be reduced.
Non-linear drive impedance at the buffer (A3) input port due in part to the non-linear component of the parasitic capacitance CD and to buffer input reflected non-linear loads will result as approximately a 1 to 1 input referred distortion current. This non-linear current would be multiplied by RF when reflected back to the output. The two-stage design described below essentially divides these distortion effects down by the gain of the first stage (A1/A1) which is much greater than one. This results in relatively superior DC through mid-band distortion.
Using two gain-stages versus one can result in a higher overall gain bandwidth product (GBWP) for the same phase margin. This results in a combination of realizing wider closed loop bandwidths (CLBW) and/or lower AC distortion. Additional benefits include the capability to improve signal to-noise performance. Any equivalent (self-generated) collector noise currents at the collector ports of Q7/Q8 are basically vector summed and 1:1 reflected back to the input as an equivalent input noise current. For 1:1 mirror action, this current can be relatively higher. With the two-stage structure, this noise current can be viewed as an equivalent input noise voltage at the second stage (A2/A2) inputs. This noise voltage is divided down by the output impedance of A1/A1 (Z1/Z1) and typically will be much higher than a single stage.
At DC and low frequencies, relatively more standing (quiescent) power is required for the single stage amplifier versus the two stage for "heavy" loads for the same buffer architecture. For heavy resistive loads and maximum voltage swing, the buffer input referred load current can determine the overall minimum standing current or power required. At low temperatures, transistor beta's are minimum, and the buffer reflected load current can be several hundred microamps. This criterion directly determines the overall minimum quiescent power attainable. Running lower equivalent standing current will result in an exponential loss in loop gain at the signal output extremes. A compounded buffer scheme can partially alleviate this condition although at the expense of reduced voltage swing. The two-stage design again divides down this buffer reflected load current by the current gain (beta) of the additional stage. This allows for relatively much lower input stage (Q3/Q4) quiescent collector current.